Latch delay optimization

For example, if a combinational logic function is shared, then the latched function call requires 1 cycle. The call delay is computed hierarchically, e.g., if the latched call to a combinational logic function represents anoth shared function, then each latched call will require 2 cycles. Since the cascaded latching is not necessary in general, optimizations can be paformed to remove the redundant latches. Such optimizations were not implemented in the current version of Hebe. 

As the statistics show in Table 5.4, the area parameters of the synthesized circuit are simply four times optimized components parameters. The delays given for these circuits are latch to latch and not input to latch as for the components hence the difference. 

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