Universal shift register

What if a different encoding has to be specified This can be done by describing each state as a vector of bits. 

In this case, the number of bits required for state encoding is dictated by the number of bits in the parameter which in this example is 3 bits. Of course, the machine state MooreState must be made wide enough to hold the new size of three bits. 

Here is a synthesis model of a 3-bit universal shift register. The universal shift register performs the following functions  

This universal register can be used as a serial-in, serial-out shift register, parallel-in, serial-out shift register, serial-in, parallel-out shift register, and as a parallel-in, parallel-out shift register. Here is the state table for the 3-bit universal shift register. 

Rightln, SO, SI, Parln, Q) input Clock, Clear, Leftln, Rightln, SO, SI input [2 0] Parln output [2 0] Q reg [2 0] Q  

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In the serial mode, the digital word (number) is sent to the computer one bit at a time. Now a binary counter provides a parallel output since each of the output bits has its own data output channel and the value of each output bit is simultaneously available. To use a serial transmission scheme, this parallel output must be put into serial form. One way to accomplish this is to use a Universal Asynchronous Receiver Transmitter (UART). The detailed operation of the UART will not be given here as it is not germane to the subject of this book. It is sufficient to say that the heart of the UART is a shift register and the shift register is strobed by a signal from the computer that displaces the binary number, bit by bit, sequentially from the register to the computer. 

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